Field of the Invention
The invention relates to a memory arrangement having a multiplicity of memory cells which are arranged regularly in a matrix form and each have a storage capacitor and a selection transistor, which are isolated from one another in the bit line direction by self-aligned insulation structures arranged orthogonally with respect thereto, and also a fabrication method for such a memory arrangement.
A dynamic random access memory (DRAM) contains a multiplicity of memory cells which are formed regularly in the form of a matrix on a semiconductor wafer. Each of these memory cells generally comprises a storage capacitor and a selection transistor. During a read or write operation, the storage capacitor is charged or discharged with an electric charge, corresponding to the respective data unit (bit), via the selection transistor. For this purpose, the memory cell is addressed with the aid of a bit line and a word line, which are arranged in row form and column form and generally run perpendicularly to one another.
The continuous trend for increasing the packing density of integrated circuits (ICs) especially including dynamic memory ICs, means that the substrate area available for an individual memory cell is reduced, which affects the electrically active elements of the memory cell (transistor, contacts, storage capacitance) as well as the insulation structures (field insulation). For trench memory cells, the trench diameter of the memory trench is reduced and so the capacitance of said trench is reduced as well, as a result of which the risk of read errors is increased. In the case of the insulation structures (field insulation), the insulation distance is reduced, thereby reducing the security of the insulation of adjacent elements. Both of these must be prevented by suitable measures.
One possible solution to these problems is to effect a suitable arrangement of the elements of the memory cells. In this arrangement, an epitaxial semiconductor layer is applied above the trench capacitors and the selection transistors are formed in this semiconductor layer above the respective trench capacitor. Since each of these two functional elements is advantageously arranged, stacked, in a different plane of the active silicon, the memory cell area does not have to be divided proportionally between these elements and can thus be configured minimally overall. What is difficult in the case of this arrangement, however, is the fabrication of the so-called strap contacts, the contact-connection of the two memory cell component parts, since these strap contacts within the semiconductor layer have a relatively high aspect ratio.
DE 199 41 148 A1 describes such a method for fabricating contacts between a trench capacitor and a selection transistor formed above the trench capacitor.
The object of the present invention is to provide a memory cell arrangement having memory cells in which a simple and space-saving contact-connection of selection transistor and storage capacitor, which are arranged one above the other, is ensured, and also to provide a method for fabricating such a memory cell arrangement.
This object is achieved by means of a method for fabricating a memory cell arrangement in accordance with claims and a memory cell arrangement in accordance with claims. Preferred developments are specified in the dependent claims.
According to the invention, a contact opening is formed in the semiconductor layer in the interspace between two memory cells that are adjacent in the bit line direction, which contact opening reaches as far as the inner electrodes of the respective trench capacitors and, after the fabrication of a collar insulator layer on the uncovered sidewalls of the contact opening, is filled with a conductive material in such a way that the inner electrodes of the trench capacitors are electrically conductively connected to the selection transistors arranged above them. Afterward, in the contact opening, an insulation opening is produced as far as a level below the upper edge of the storage capacitors and is filled with an insulator, as a result of which the electrically conductive layer in the contact opening is subdivided into two partial regions that are insulated from one another, so that each of the partial regions forms a strap contact which electrically connects the inner electrode of the trench capacitor to the selection transistor of the respective memory cell.
What is significantly advantageous in the case of the method according to the invention or the structure according to the invention is that the strap contacts, which are initially fabricated as one contact point, are only separated by the formation of the trench insulation in this contact point. The wider contact hole of the contact point has a significantly more favorable aspect ratio for processing than two separate contact holes, as a result of which the process complexity is reduced. Furthermore, very narrow strap contacts and strap insulations can be fabricated by the method according to the invention in comparison with the conventional methods.
Since the formation and the filling of the contact hole is effected in a self-aligned manner with respect to the word lines or the insulation encapsulations of the word lines of the two memory cells, complicated method steps can be obviated.
In accordance with an advantageous embodiment, an opening with a funnel-shaped profile is produced by anisotropic etching of a spacer layer deposited on the electrically conductive layer in the contact opening, the width of the opening decreasing with depth. In the subsequent process steps, the patterned spacer layer serves as a mask for the fabrication and filling of the insulation opening in the electrically conductive layers of the contact opening. This obviates a photolithographic mask step for fabricating and filling the insulation opening. The thickness of the spacer layer, which can be set very precisely, determines very exactly the width of the etched opening and the width of the insulation opening produced underneath. At the same time, this also enables the width of the strap contacts to be determined very precisely. In particular, however, this method enables insulation openings whose width is narrower than the minimum possible lithographic web width.
In an advantageous embodiment of the invention, a thin collar insulator layer is produced at the uncovered sidewalls of the semiconductor layer in the contact opening. This insulator layer serves as insulation of the electrically conductive layer in the contact opening with respect to the semiconductor layer. This avoids leakage currents which could discharge the trench capacitor.
In an advantageous embodiment of the invention, the thin collar insulator layer is produced in the contact opening with the aid of an insulation step. This method has the advantage that a uniform insulator layer can thus be produced very simply, this being difficult to do with the layer deposition method usually used in particular at the steep-edged sidewalls of the semiconductor layer.